Automatic Transfer Scheme Design for MV Switchgear: Logic, Timers and Blocking

An MV automatic transfer scheme (ATS) must restore an unfaulted bus without ever closing an alternative source onto a bus fault, an out-of-phase residual motor voltage or an already energised section. The difficult work is not drawing an undervoltage relay and two timers; it is building a deterministic state machine from primary topology, source capability, protection actions, motor dynamics, breaker performance and credible instrument/control failures.

This guide covers two-source MV switchboards with an incomer/coupler or main–tie–main arrangement. Values are not universal: settings and transfer method must come from the actual load-flow, short-circuit, motor-transfer, stability, protection and DC studies.

Executive rules

Separate source loss from bus fault; transfer only the former.
Define open, fast, in-phase, residual-voltage, fixed-delay and closed transition explicitly—“fast transfer” is not a complete specification.
Do not treat lost VT/fuse as dead bus or failed source.
Use breaker actual position/current and healthy voltage sources; a command issued is not an operation completed.
Block transfer for busbar/arc protection, breaker failure, lockout, invalid topology, synchronism failure and other project hazards.
Coordinate every timer with relay detection, breaker opening/closing time, motor residual voltage and process ride-through.
Make the sequence one-shot with clear abort, fail, reset and power-recovery states.
Test every valid, forbidden and failure transition end-to-end.

1. Standards and evidence hierarchy

Reference/evidence	Application
IEC 62271-200:2021+AMD1:2024	MV metal-enclosed assembly/interlock context
IEC 62271-100:2021+AMD1:2024	Breaker operating characteristics and mechanism interfaces
IEC 61850-5:2013+AMD1:2022	Communication requirements for power-utility automation functions/device models
IEC 61850-6:2009+A1:2018+A2:2024	SCL configuration exchange and functional relationships
IEEE 3004.8-2016	Motor protection and motor-bus-transfer considerations in industrial/commercial systems; a revision project is active
IEEE C37.2-2022	Device function numbers, acronyms and contact designations
Project studies/manufacturers	Source/load dynamics, motor data, breaker time, relay measurement/logic and DC performance

No single listed standard supplies a complete ATS setting set. The approved operating philosophy and studies are the design basis; equipment standards and manuals constrain implementation.

2. Freeze topology and modes

normal source and alternate source for each bus section;
normally open/closed coupler and permitted main–tie–main breaker combinations;
whether sources may ever parallel and for how long;
utility, transformer, generator and embedded-generation interfaces;
source/bus VT locations and selection;
earthing arrangement in each topology;
load shedding and single-source capacity;
manual, automatic, maintenance/test and emergency modes;
automatic return, manual return or no return after transfer.

Create a truth table of all breaker/truck/earth-switch states. Any state not explicitly valid is invalid; the ATS must not infer a safe route through contradictory 52a/52b or intermediate positions.

3. Transfer-method taxonomy

Method	Closing criterion	Main concern
Open fixed-delay	Normal source open; wait set delay; alternate close	Process interruption and motor residual voltage may still be significant
Residual-voltage	Close after bus voltage decays below studied magnitude	Frequency/phase at close and motor reacceleration
In-phase / synchronised open transfer	Predict next acceptable phase window after source opens	Measurement, breaker close-time scatter and algorithm performance
Fast transfer	Open then close before bus phase departs approved envelope	Detection/open/close time and out-of-phase torque
Closed transition	Synch-check then momentarily parallel before opening old source	Source permissions, fault level, circulating power and parallel duration
Manual transfer	Operator sequence under same safety/synchronism rules	Human factors and bypass control

A scheme may attempt fast transfer first, then fall back to in-phase or residual-voltage transfer. Each window, fallback and timeout must be explicit. Closing onto a decaying motor bus is a transient electromechanical event; use a motor-bus-transfer study, not a generic 20% residual threshold.

4. Initiating source-failure logic

three-phase undervoltage with phase supervision and appropriate pickup/dropout;
underfrequency/frequency-rate or source relay status where justified;
upstream breaker/transformer trip or source-available contact;
incoming current/power plausibility to distinguish VT loss;
VT MCB/fuse, VT position and measurement-quality supervision;
minimum persistence timer to ride through transients without delaying genuine failure excessively;
valid topology and ATS armed/automatic mode;
alternate source healthy and capacity available.

Use multiple evidence where consequence requires it. A single phase VT fuse can resemble undervoltage; all-phase VT loss can resemble a dead bus. A transfer triggered by instrument failure can parallel sources or interrupt a healthy bus.

5. Bus-fault discrimination and blocking

ATS must not re-energise a faulted bus. Typical transfer blocks include:

busbar differential/check-zone trip or bus lockout;
internal-arc detection/protection operation;
incomer/coupler breaker-failure operation;
feeder protection indicating a fault not isolated from the bus, as defined by the study;
transformer differential/REF or source lockout where alternate energisation is unsafe;
earth switch closed, truck invalid, access/maintenance key state;
loss of critical DC, VT, synchronism measurement, IED/network or interlock validity;
operator emergency stop, ATS out-of-service or test mode;
failed prior transfer or unresolved breaker-position mismatch.

Not every feeder trip should block transfer: if the feeder breaker has cleared an external feeder fault and the bus is healthy, transfer may remain legitimate. Define the block matrix by fault location and clearing sequence.

6. Deterministic state machine

Disarmed/healthy: topology monitored, no automatic action.
Armed: normal topology, both source/VT/control prerequisites valid.
Source-fail validation: qualifying failure persists; blocks checked.
Open old source: trip command issued and supervised.
Prove separation: 52a/52b, current and/or isolating state proves old source removed.
Select transfer window: fast, in-phase, residual or delayed criterion.
Close alternate path: final topology/synchronism/dead-bus/interlock check immediately before output.
Prove energisation: breaker closes, bus voltage/current valid and no immediate protection operation.
Complete: load shed/restart plan active; automatic sequence locked out from repeat.
Abort/failed: outputs removed, alarm/lockout latched, manual recovery required.

Every transition needs entry conditions, action, completion proof, timeout and fallback. Store sufficient state through brief control-power dips only if safe; after an uncontrolled reboot, reconstruct topology from valid measurements rather than resuming a stale step.

7. Timer engineering

Timer	What determines it	Risk if wrong
Source-fail validation	Voltage dips, protection clearing and process ride-through	Nuisance transfer or slow restoration
Old-breaker open timeout	Trip output + breaker opening tolerance + position/current dropout	Close before separation or needless abort
Fast window	Motor/source angle trajectory and breaker close time/scatter	Out-of-phase close
Residual threshold/timeout	Motor aggregate decay and allowable reconnection transient	Torque/current damage or excessive outage
Alternate close timeout	Output + close-circuit + breaker closing tolerance	Repeat command/ambiguous state
Post-transfer settle	Voltage recovery, motor reacceleration and protection transients	Premature load restore/retransfer
Return-source healthy	Source stability and operating policy	Hunting between sources

Use worst-case guaranteed/verified breaker times at relevant control voltage, not only average commissioning values. Include relay input/output, interposing contact, communication and measurement-filter delay. Timer tolerance and scan/processing resolution are part of the budget.

8. Breaker position and current proof

52a/52b provide mechanism position but can disagree, bounce or share a linkage.
Current dropout proves source current ceased but a lightly loaded or dead source may have near-zero current before opening.
Bus/source voltage proves electrical condition but VT failure can mislead.
Use the studied combination and a transition allowance; invalid proof aborts rather than assumes open.
For drawout breakers, require valid service/test position and secondary plug state.
A failed-to-open old source must initiate the defined breaker-failure/transfer-abort action before any alternate close.

9. Synchronism and motor residual voltage

After source loss, induction and synchronous motors can sustain a bus voltage whose magnitude, frequency and phase drift relative to the alternate source. An out-of-phase reconnection can impose severe motor torque, shaft stress and current. The study should model motor mix/inertia, load torque, capacitors, generators, transformer impedance and breaker times.

Define acceptable voltage magnitude, frequency/slip and phase angle at contact touch.
For predictive in-phase transfer, compensate measured slip and breaker closing time including scatter.
For residual transfer, demonstrate that the selected magnitude/angle criterion limits transient duty.
Check phase sequence and VT scaling/wiring.
Block on invalid/lost voltage; do not infer residual decay from elapsed time alone unless the study justifies fixed delay.
Test algorithm performance using a dynamic simulator or playback representative of studied trajectories.

10. Alternate-source capacity and load management

transformer/generator/cable continuous and short-time capacity;
pre-transfer loading and available spinning/reserve capacity;
motor inrush/reacceleration and bus voltage recovery;
essential/nonessential load priorities and shed groups;
load shed before close, immediately after close or adaptive based on source margin;
failed feeder-to-open response;
staggered motor/load restoration and operator authority;
underfrequency/undervoltage backup and protection coordination in single-source topology.

11. Return transfer and anti-hunting

Return to the preferred source may be manual, open automatic or closed transition. Require stable-source voltage/frequency for a studied dwell time, clear all blocks and confirm process permission. Use one return attempt, minimum time on alternate source and lockout after failure to prevent repeated oscillation. Closed return additionally needs paralleling permission, synch-check, fault-level capability and a strict overlap timeout with fail-to-open action.

12. Control power, communications and common modes

ATS controller/IED power during loss of one bus/source and at minimum DC.
Independent trip and close supplies/routes required by the protection philosophy.
Simultaneous coil voltage drop and breaker timing.
Hardwired/GOOSE signal stale, loss and test/simulation behaviour.
Network switch, time source and configuration common failures.
Inter-panel common terminal/fuse/MCB and cable-route failures.
Cyber access to modes, blocks, settings and remote commands.
Watchdog/power-cycle output state and sequence recovery.

13. Operator modes, bypass and reset

Show Armed, Blocked, In Progress, Complete, Failed and Maintenance/Test distinctly.
Display normal/alternate source health, bus voltage, breaker validity and first blocking cause.
Manual commands must obey primary interlocks and synchronism unless a separately governed emergency procedure exists.
Temporary blocks/bypasses require authority, alarm, time limit and restoration evidence.
Reset clears sequence latch only after actual topology and fault/lockout cause are safe.
Do not permit a remote reset to re-arm onto an unresolved busbar/arc trip.
Record settings/mode/bypass changes and sequence SOE with reliable time.

14. FAT/SAT scenario matrix

Validate the state diagram, Boolean logic and timer budget independently against studies.
Test normal source failure by voltage, upstream trip and combined evidence.
Inject single/all-phase VT fuse failure and confirm no false transfer/dead-bus permission.
Test busbar, arc, transformer, feeder and breaker-failure trips against the exact block matrix.
Force old breaker fail-to-open, slow-open, position disagreement and residual current.
Exercise fast/in-phase/residual/delayed windows with dynamic voltage playback.
Force alternate breaker fail-to-close, slow-close, trip-during-close and immediate post-close fault.
Remove DC feeds, commons, IED power, network paths and time source at every sequence state.
Test alternate overload, load-shed failure and motor restoration.
Verify manual/auto/maintenance modes, concurrent commands, one-shot, abort, reset and reboot recovery.
Test automatic/manual return, source instability and anti-hunting.
Capture end-to-end waveforms, SOE, breaker travel/contacts and bus voltage; reconcile as-built settings/documents.

15. Frequent mistakes

Mistake	Consequence	Correction
Undervoltage alone starts ATS	VT loss/bus fault causes unsafe transfer	Source/VT/fault discrimination
Trip command assumed open	Alternate parallels failed old source	Prove separation/abort on timeout
Generic residual-voltage setting	Motor torque/current damage	Dynamic motor-bus study
Nominal breaker time used	Missed phase window	Use tolerance/voltage-dependent verified time
All protection trips block ATS	Needless outage	Fault-location/clearing block matrix
Controller resumes stale step	Unexpected close after power return	Safe state reconstruction
Only successful transfer tested	Abort/failure defects latent	Fault insertion in every state

16. Design-release checklist

Topology, modes and source-parallel policy approved?
Transfer method and fallback windows study-backed?
Source failure distinguished from VT loss and bus fault?
Complete block/abort matrix approved?
Old-source separation and alternate-close proofs deterministic?
Timer budget includes relay, communication and breaker tolerances?
Motor residual/reacceleration and alternate capacity validated?
DC/network/common-mode and reboot behaviour safe?
One-shot, return and anti-hunting philosophy defined?
Operator modes/bypass/reset governed?
FAT/SAT includes dynamic playback and inserted failures?
Settings, logic, SCL, drawings and test evidence baselined together?

References and further reading

Engineering note: Thresholds/timers require project studies and verified equipment data. This framework is not a substitute for a motor-bus-transfer or synchronism study.