MV Busbar Protection Explained: High-Impedance, Low-Impedance and Zone-Selective Interlocking

An MV bus fault must be cleared by every source connected to the faulted zone, yet an external feeder fault must remain selective even when one CT saturates. High-impedance differential, low-impedance numerical differential and zone-selective interlocking (ZSI) solve different parts of that problem; they are not three interchangeable settings.

This guide compares their operating principles, CT and wiring requirements, topology logic, trip zones, failure modes, calculations and tests. It also covers partial differential and hybrid schemes for industrial double-ended switchgear.

Executive comparison

Scheme	Primary decision	Strength	Main constraint
High-impedance differential (87B)	Voltage/current in a parallel CT secondary circuit	Fast, simple and highly stable for external CT saturation when engineered correctly	Matched dedicated CTs, fixed ratio, wiring/stabilising-voltage/overvoltage design
Low-impedance differential (87B)	Numerical operate current versus restraint from separate CT inputs	Flexible zones/ratios, diagnostics and complex bus configurations	CT saturation algorithm, topology replica, input/channel and configuration complexity
ZSI/blocking	Upstream overcurrent accelerates unless downstream pickup blocks it	Cost-effective speed improvement using feeder/incomer relays	Not true KCL differential; pickup, blocking latency and communications/failure mode govern
Partial differential	Sums selected source/tie currents around a partial zone	Useful where feeder CT inputs are unavailable	Cannot inherently distinguish all downstream faults; often needs ZSI/blocking

1. Define the bus zone before choosing a relay

Draw every incomer, feeder, bus coupler, bus riser, transformer/generator and DER source.
Place each CT physically on the one-line and mark primary polarity. The protected zone ends at CT locations, not breaker symbols.
Identify blind/end zones between CT and breaker contacts, cable terminations and source-side compartments.
Define normal, coupler-closed, transfer, maintenance, test and future-extension states.
Define which disconnectors/isolators can change zone membership and how their positions are acquired/supervised.
Produce a trip matrix for each bus zone and breaker-failure escalation.
Overlap adjacent protection zones or provide dedicated end-fault/dead-zone logic; never leave an unprotected gap.

For a simple bus with consistently oriented CTs, Kirchhoff’s current law gives an ideal differential quantity I_diff = |ΣI_k,signed|. Load and external fault currents sum to zero; internal-fault source currents sum into the zone. Real CT error, saturation, wiring and channel/time error create spill that the scheme must restrain.

2. Standards position in 2026

IEEE 3004.11-2019 is the directly relevant recommended practice for industrial/commercial bus and switchgear protection.
IEC 60255-1:2022 provides common protection-equipment requirements; IEC 60255-26:2023 and 60255-27:2023 cover EMC and product safety.
IEC 61869-2:2012 governs inductive CT requirements used in bus schemes.
IEC 62271-200:2021+A1:2024 governs the MV metal-enclosed assembly and IAC classification/test framework.
IEC 61850 applies to GOOSE, process-bus/SV and station engineering when used.

As of August 2026, IEC 60255-187-2 (functional requirements for low-impedance busbar differential protection) remains a standards project rather than a published IEC International Standard. Do not cite a draft as an issued requirement. Use the published standards, exact relay manual and project performance specification.

3. High-impedance differential principle

All CT secondaries of one phase are paralleled with matching ratios/polarities. For load or an external fault, their secondary currents circulate and ideally leave little current through the high-impedance relay branch. If one external-fault CT saturates, the stabilising impedance forces a voltage that limits false relay current. For an internal fault, all CTs drive current toward the relay branch and develop operating voltage.

A common screening stability voltage for one completely saturated CT branch is of the form V_stab ≈ I_through,sec(R_ct + R_lead,path). The exact multiplier/lead path and safety factor depend on star-point/junction topology and relay manufacturer; use the approved scheme equation.

Select relay/stabilising resistor operating voltage above maximum external-fault stability voltage with relay/CT/temperature/study margin.
At that voltage, sum excitation current of every parallel CT plus relay-branch current. Referred to primary, this determines minimum internal-fault sensitivity.
Specify CT knee point, maximum hot secondary resistance and maximum excitation current at stated voltage(s)—typically an IEC PX-style parameter set.
Calculate peak/energy during internal fault and select a nonlinear resistor/MOV to limit dangerous secondary voltage without impairing operation.
Check stabilising resistor thermal/voltage rating, insulation, creepage, terminal block and test-switch duty.
Use dedicated, well-matched CTs and controlled secondary star point/single earth. Added burden or wrong tap can defeat the design.

4. High-impedance worked screening example

Illustrative only. Maximum external through fault is 20 kA primary with 1,000/1 A CTs, giving 20 A secondary. Worst saturated-branch hot R_ct is 3.0 Ω and lead path to the junction is 1.5 Ω under the selected scheme convention. A screening stability voltage is 20 × (3.0 + 1.5) = 90 V.

If the manufacturer/project factor leads to a 120 V operating setting, evaluate excitation current of every CT at 120 V from certified curves.
With six CTs each drawing 8 mA and relay branch drawing 100 mA, secondary sensitivity is 6×0.008 + 0.100 = 0.148 A, or ideally 148 A primary before study margins.
Verify the specified knee point/curve supports 120 V with required margin; do not apply a generic “2×Vset” rule without the relay/standard design method.
Calculate maximum un-clamped internal-fault voltage and MOV/resistor energy for the real fault duration.

The example proves only arithmetic structure. Final stability uses maximum fault/X/R, CT/lead resistance at temperature, exact junction geometry, relay impedance/tolerance and CT excitation curves.

5. High-impedance advantages and disadvantages

Advantages	Disadvantages
Fast and conceptually transparent	Same ratio and closely matched dedicated CTs normally required
Excellent stability for severe single-CT saturation when correctly designed	CT circuit is one interconnected protection network; maintenance changes are sensitive
Few relay inputs and no dynamic topology algorithm for a fixed zone	Complex reconfigurable buses require separate zones/CT switching and careful isolation
Long service history and clear electrical calculations	High secondary voltage needs MOV/insulation/safety controls
Can be economical for a simple single zone	Limited metering/phasor diagnostics and harder future extension

6. Low-impedance numerical differential principle

Each bay CT connects to a separate analogue or SV channel. The relay scales/polarity-corrects currents, assigns bays to zones and calculates operate and restraint quantities. A generic percentage characteristic is:

Operate when I_diff > I_min + Slope × I_rest, possibly with multiple slopes/high-set stages.

I_rest may be maximum, sum or another relay-specific function; the characteristic and CT-saturation detector are not transferable between vendors. High restraint improves external-fault security but can reduce sensitivity; the setting study must use the exact equation.

Imin: above maximum standing differential from CT ratio/phase, cable and channel error yet below minimum internal fault.
Slope(s): secure for maximum external through fault and unequal CT saturation, with approved CT dimensioning.
High-set/unrestrained: fast internal clearing but must be secure for the worst external CT saturation and switching/transient.
CT saturation logic: prove with dynamic waveforms; vendor algorithms use different pre-saturation/external-fault evidence.
Open-CT supervision: alarm/block selected zones without masking a real fault; distinguish wiring failure from evolving internal fault.
Check zone: an independent overall differential/check criterion can supervise dynamic bus-zone selection.

7. Bus replica and dynamic zone selection

For double-bus or transferable bays, disconnector positions determine which currents belong to which zone. Wrong position status can trip the healthy bus or exclude the faulted bay.

Use both open and closed indications where available; treat “neither/both” as invalid rather than guessing.
Define current assignment during disconnector travel and breaker/disconnector operation sequence.
Supervise isolator auxiliary contact discrepancy and station-process communication quality.
Use check zone, zone overlap and controlled blocking for invalid topology.
Capture first-out topology and currents before the trip changes auxiliary contacts.
Test every legal and illegal switching combination, including maintenance bypass and future bays.

8. Low-impedance advantages and disadvantages

Advantages	Disadvantages
Different CT ratios can be scaled within approved limits	Many inputs/MUs and more configuration
Flexible multiple zones and bus replicas	Topology-data failure becomes a protection failure mode
Rich metering, CT supervision and event records	Security depends on proprietary saturation/restraint logic
Easy trip-matrix/BF/end-zone integration	Firmware/SCL/network/time lifecycle must be controlled
Well suited to complex sectionalised/double bus	Common relay/central unit can affect many zones unless redundant architecture is used

9. Zone-selective interlocking (ZSI)

In a typical blocking ZSI scheme, a downstream feeder relay that picks up sends a block to the upstream incomer/coupler. The upstream relay delays for a downstream fault but trips rapidly when it sees high current and receives no timely downstream block—consistent with a bus-zone fault. ZSI improves overcurrent speed while retaining feeder selectivity.

Define which feeder functions send block: phase, earth, arc, directional and/or high-set.
Set upstream fast pickup below the minimum bus fault but above maximum load/inrush/security threshold.
Ensure every downstream fault that makes upstream fast element pick up also produces a block; CT/sensor/pickup reach must overlap.
Budget downstream detection + logic + output/GOOSE + network/input time to arrive before upstream relay commit/decision.
Choose fail mode deliberately: loss of block may cause fast upstream trip (dependable but less selective) or slow operation (selective but higher bus arc energy).
Use downstream breaker status/BF logic to release/retain block appropriately; a stuck feeder breaker must escalate upstream.
Test simultaneous faults, feeder relay out of service, communications loss and settings-group mismatch.

10. What ZSI cannot do

It does not apply KCL to a precisely bounded bus zone.
It can be blind if the bus fault is below upstream pickup or current is limited by grounding/arc impedance.
It may misclassify a downstream fault when the downstream relay/CT/channel fails to assert block.
It cannot inherently distinguish an incomer cable/source-side fault from a bus fault.
It does not remove breaker time, BF or arc-resistant/hazard requirements.
It is often an excellent complement/backup to differential or a practical improvement where full 87B is unavailable—not a universal equal substitute.

11. Partial differential and hybrid protection

A partial differential zone may sum incomer and tie currents while excluding individual feeder CTs. It detects current leaving the source-defined zone but can also see downstream feeder faults. Feeder ZSI/blocking can restrain partial differential for a downstream fault, allowing fast operation when no block exists. This can be effective in double-ended industrial substations but requires the blocking arrival before the differential commits.

Document exactly which CTs define the partial zone in coupler-open/closed states.
Calculate external feeder fault current seen as operate current and ensure blocking coverage.
Define behaviour if a feeder relay is removed/tested or communications fails.
Retain independent time-overcurrent backup and BF escalation.
Do not describe a source-sum scheme as “full bus differential” in drawings or hazard studies.

12. Ground-fault coverage

Phase differential sensitivity may be insufficient for an MV bus earth fault in resistance, isolated or resonant grounding. Model zero-sequence source and CT arrangement. Options include sensitive phase differential, separate neutral/ground differential, arc-light plus sensitive current, neutral overcurrent/directional earth fault or dedicated compartment sensors. Confirm the trip removes every ground source.

13. Trip matrix, BF and close blocking

Trip all incomers, coupler and backfeeding feeder/generator breakers connected to the selected faulted zone.
Initiate BF separately for every commanded breaker and escalate to the next isolation boundary.
Handle end-zone fault where breaker opens but current persists through a CT-to-breaker section.
Latch bus trip/lockout and block automatic transfer, autoreclose and remote/local close until inspection/reset.
Send upstream transfer trip where the local breaker cannot isolate a source-side/cable fault.
Use independent trip circuits/outputs/DC where the reliability study requires it.
Record zone, check-zone, CT saturation, topology, first-out and all trip/BF targets with synchronized SOE.

14. CT and process-bus requirements

High impedance: ratio/polarity match, PX parameters, low leakage reactance, hot Rct, excitation curve and controlled leads.
Low impedance: ratio/phase/transient performance at maximum through fault/X/R, matched time response and relay-specific dimensioning.
SV: channel scale/polarity, MU range, time alignment, quality, stream loss, network redundancy and common-mode failure.
Location: CT on one side of breaker changes end-zone/overlap and BF logic; verify physical drawing.
Maintenance: shorting/test facilities must not open a live conventional CT or silently remove a bay from differential.

15. FAT/SAT dynamic test matrix

Verify CT ratio/polarity/core/lead resistance and zone boundaries through final wiring.
Inject normal load and maximum expected standing spill; confirm no operation and correct metering.
Test internal faults at minimum pickup, high current, every phase and earth-fault condition.
Test external faults with one CT saturated, progressive saturation, DC offset, maximum X/R and remanence.
For high impedance, verify relay/stabilising/MOV circuit, operating voltage, stability and insulation safely.
For low impedance, test every slope/high-set boundary, CT-open supervision and evolving external-to-internal fault.
Exercise every disconnector/breaker state, invalid topology, zone overlap, check zone and bus-coupler arrangement.
For ZSI, measure block path versus upstream commit at pickup/timing extremes; fail every link/input/feeder relay.
Trip every zone through final breakers; verify all-source isolation, BF, transfer trip, lockout and close/ATS block.
Test relay/MU/DC/network/time/redundancy failure and maintenance/test modes.
Capture SOE/COMTRADE and compare first-out/topology with injected event.
Perform live-load primary phasor/polarity/stability check before enabling trip.

16. Selection framework

Project condition	Likely direction
Simple fixed single bus, matched dedicated CTs	High impedance can be robust/economical
Sectionalised/double bus, varied CT ratios, rich diagnostics	Low-impedance numerical differential
Existing feeder/incomer relays, no spare CT inputs, moderate risk	ZSI/blocking with rigorous failure study
Only source/tie CTs available	Partial differential plus ZSI/overcurrent; label limitations
High arc-flash consequence/critical bus	Full differential plus arc-light and independent backup
Very low ground-fault current	Add grounding-specific sensitive/optical protection

17. Frequent mistakes

Mistake	Consequence	Correction
Zone drawn at breakers, CTs omitted	Blind/overlap fault mishandled	Physical CT-boundary drawing
High-Z knee point only	Stability/sensitivity/voltage unproven	Full resistance/excitation/MOV design
Low-Z slope copied	Saturation security unknown	Exact relay equation/dynamic study
ZSI called differential	Coverage overstated	Document pickup/blocking limits
Lost block ignored	Fast upstream overtrip or slow bus trip	Explicit fail mode and alarm
Coupler CT/zone not modelled	Wrong bus remains energised	All states and trip matrix
Steady injection only	CT saturation/topology races latent	Dynamic multi-bay tests

References and further reading

Engineering note: The numerical formulas are conceptual. Final settings and CT/stabilising/MOV calculations must use the selected relay’s scheme manual, actual wiring geometry and approved maximum/minimum fault studies.