Protection Relay Secondary-Injection Testing During FAT

Secondary injection can prove relay settings, measurement, logic and outputs with high precision—but only inside its declared test boundary. Injecting directly at an IED terminal does not verify CT/VT ratio, field wiring or primary polarity; stopping at a relay trip LED does not verify the breaker trip path.

This guide builds a rigorous MV switchgear relay FAT under IEC 60255. It covers configuration freeze, parameter- and system-based tests, current/voltage/binary injection, pickup/dropout/timing, curves, directional/differential/voltage/frequency functions, scheme logic, GOOSE/Sampled Values, tolerances, breaker operation, event records, change control and restoration.

Executive conclusions

• Freeze and read back the installed settings, logic, I/O, firmware, SCL and active setting group before test.
• Define the injection boundary and excluded equipment on every report.
• Use parameter-based tests to verify individual elements and system-based scenarios to verify interaction/logic; neither alone covers everything.
• Test pickup, dropout/reset, operate time, curve shape, direction, restraint and blocking as applicable—not one point per function.
• Separate relay algorithm time, output-contact time, breaker opening time and total scheme time.
• Check CT/VT primary-secondary scaling, frequency, phase sequence and zero-sequence calculation before judging elements.
• Use the actual trip matrix and verify each output through lockout/interposing/DC coil/breaker where FAT scope permits.
• For IEC 61850, test normal GOOSE/SV plus quality, test/simulation flags, subscription loss, time and network failure.
• Apply declared relay and test-set tolerances with an agreed conformity rule; do not compare displayed rounded values as exact.
• Remove every force, test mode, output block and temporary setting, then read back the as-left file/checksum.

1. Test boundaries

Injection point	Included	Excluded
IED analogue terminal	Relay input/algorithm/logic/output	CT/VT, test block and field wiring
Panel test block	Test block-to-IED wiring plus relay	Primary CT/VT transformation
Merging-unit SV input	Digital data/IED algorithm	Sensor/MU analogue chain if simulated
Physical relay output to breaker	Relay output, DC path, coil, breaker/feedback	Protection analogue primary chain unless separately tested
GOOSE message simulation	Subscriber logic/output path	Real publisher input/logic unless end-to-end

Combine staged tests for diagnosis with end-to-end tests for confidence. Label every result so a simulated internal bit is not mistaken for primary-chain proof.

1A. Risk-based coverage strategy

Do not copy every possible setting into hundreds of low-value points, and do not sample away critical logic. Build coverage by requirement and risk:

• one or more boundary points for every enabled measuring element;
• multiple points across every inverse, differential/bias, distance or directional characteristic used for coordination;
• every trip output, breaker/coil channel and lockout destination;
• every permissive, block, setting-group, autoreclose and breaker-failure branch;
• all CT/VT/phase/residual input mappings and normal/degraded measurement states;
• each communication-based trip/interlock and its loss/bad-quality response;
• representative repeated points to confirm phase consistency and timing scatter;
• full testing of design variants; sample identical feeders only with proven configuration identity and failure escalation.

A requirements traceability matrix should show why each test exists and which untested combinations are covered by design identity or prior evidence. “Automated 100% pass” is meaningless if the template never exercised a disabled high-set or wrong output mapping.

2. Inputs and configuration freeze

• approved protection study and settings schedule;
• relay native settings and human-readable comparison report;
• firmware/hardware/modules and manufacturer manuals;
• CT/VT ratios, cores, polarity and wiring diagrams;
• trip/cause-effect matrix and interlocking philosophy;
• binary I/O, LEDs, HMI, alarm/SOE and disturbance-record settings;
• active setting group and group-change logic;
• SCD/CID, GOOSE, Sampled Values, report and time configuration;
• test template/equations/tolerances and test-set calibration;
• open deviations, disabled elements and expected future site settings.

Read back the configuration from the installed IED and calculate a checksum. Compare values including hidden/default logic and scaling—not only protection pickups visible on a summary sheet.

3. Safety and test facilities

• Primary equipment de-energised/controlled for breaker operations.
• CT side shorted before relay side is opened; CT short removed only after reconnection.
• VT source isolated before secondary voltage injection to prevent backfeed.
• Test-set neutral/earth and panel PE arranged to avoid loops/shorts.
• Voltage/current outputs off before lead changes.
• Trip outputs blocked only under a controlled register when breaker operation is not intended.
• Remote/intertrip/GOOSE outputs isolated from adjacent live equipment.
• Breaker operation count, mechanism state and moving-part boundary controlled.
• Every temporary link/force/test mode independently cleared at completion.

4. Test-set configuration

• nominal secondary current/voltage (1 A or 5 A; 100/110 V arrangements);
• primary-secondary scaling and √3/residual conventions;
• system frequency and phase rotation;
• current/voltage source ranges, compliance and output burden;
• binary input wet/dry thresholds and debounce;
• binary output rating/polarity and DC wetting source;
• time reference/sample rate and trigger definition;
• GOOSE/SV interface, VLAN/APPID/MAC/dataset and test/simulation flags;
• template/XRIO/model version and manufacturer tolerance data;
• test-set/software/firmware serial/calibration.

OMICRON’s current CMC 500 official information describes modular multi-phase current/voltage sources and parameter-based Test Universe plus system-based RelaySimTest approaches, including GOOSE, MMS and Sampled Values. Test capability does not validate a template automatically; review every mapping and tolerance.

5. Metering and plausibility first

• Inject balanced three-phase nominal quantities.
• Verify relay RMS magnitudes, angles, frequency, phase sequence and primary display.
• Inject one phase at a time to prove channel mapping.
• Verify residual/negative/zero-sequence quantities from controlled unbalance.
• Check power direction, P/Q sign and phase-earth/phase-phase voltage conventions.
• Verify HMI/SCADA values, units, scaling and deadbands.
• Resolve metering/scaling/polarity errors before protection timing tests.

6. Pickup, dropout and reset

1. Hold non-tested polarising/restraint quantities at defined values.
2. Ramp or step the operating quantity from below pickup at an approved rate.
3. Record pickup from element state, not final trip if intentional delay exists.
4. Increase safely above pickup, then decrease to record dropout/reset.
5. Calculate dropout/pickup ratio where relevant.
6. Repeat phases and directional quadrants/setting groups as required.
7. Apply relay accuracy plus test-set uncertainty to the acceptance decision.

A very slow ramp can interact with filtering/memory; a coarse step can overstate pickup precision. Use the relay/test-module method and preserve step size/ramp rate.

7. Definite and inverse-time tests

• Test below pickup/no trip, just above pickup and representative high multiples.
• For definite time, measure element and output contact separately where needed.
• For inverse curves, test several current multiples spanning coordination range.
• Use the exact IEC/IEEE/manufacturer curve family, time multiplier/dial and minimum time.
• Account for intentional start/operate/reset and breaker/output delay.
• Verify high-set instantaneous/short-delay transitions.
• Check curve crossing/coordination points relevant to the protection study.
• Preserve calculated expected time and tolerance source.

8. Directional elements

• Verify voltage/current polarising channels and phase rotation.
• Test forward and reverse faults at equal magnitudes.
• Sweep operating angle around characteristic boundaries.
• Test minimum polarising voltage/current and memory polarisation where used.
• Test close-in/zero-voltage behaviour and directional earth-fault residual quantities.
• Verify reverse direction blocks output and generates expected start/status.
• Check CT/VT polarity and P/Q sign before changing relay characteristic.

9. Differential and REF tests

• Confirm CT ratios, vector/phase compensation and protected-zone mapping.
• Inject equal through current to prove stability/restraint.
• Inject internal differential current to prove pickup/operate.
• Test slope/bias characteristic at multiple restraint levels.
• Test high-set/unrestrained stage and harmonic/other restraint if applicable.
• For REF, verify neutral/phase CT polarity and stabilising principle.
• Test CT saturation/open-circuit supervision logic by approved secondary simulation.
• Record differential and restraint quantities displayed by relay.

10. Voltage, frequency and thermal functions

• 27/59 phase-earth/phase-phase pickup, delay, hysteresis and fuse-failure blocking.
• 59N/residual voltage scaling and earth-fault/VTS discrimination.
• 81U/O frequency pickup/delay and voltage supervision.
• 81R/ROCOF ramp rate, window/filter and islanding logic.
• 46 negative-sequence current calculation and delay.
• 49 thermal model heating/cooling, preload, reset and alarm/trip.
• Loss-of-load/undercurrent/power functions where used.
• Setting-group or motor start/restart logic interactions.

11. Logic and scheme tests

• breaker failure: current/no-current supervision, retrip, timer and correct backup outputs;
• autoreclose: shots, dead/reclaim time, block/lockout, synch-check and unsuccessful close;
• 86 lockout: trip, latch, reset permissive and close block;
• synch-check: voltage, angle, frequency slip, dead/live conditions and timeout;
• intertrip/permissive: send/receive, channel supervision and failure state;
• bus transfer/selector logic: source availability, interlocks and no unintended paralleling;
• trip matrix: every element to correct coil/breaker/alarm;
• setting-group logic: source, priority, indication and change under load.

12. Output path and breaker operation

1. Inject the actual protection quantity at the panel test block where possible.
2. Observe element pickup/operate, logic and selected relay output.
3. Measure output/interposing/86 and trip-coil voltage/current.
4. Verify correct breaker opens and other breakers remain unchanged.
5. Confirm 52a/52b, TCS, lockout and breaker-failure current reset.
6. Verify alarm/target/HMI/SCADA/SOE/disturbance record.
7. Record relay time, output time, breaker time and total end-to-end time separately.

13. IEC 61850 GOOSE and Sampled Values

• Verify SCD/CID revision and publisher/subscriber mapping.
• Inject/subscribe to exact dataset members and quality attributes.
• Test test/simulation mode so test messages cannot operate normal plant unintentionally.
• Measure end-to-end application response, not Ethernet frame latency alone.
• Open one network path and verify PRP/HSR/design redundancy.
• Test lost/stale/bad-quality subscription alarm/fail-safe logic.
• For SV, verify sample rate, synchronisation quality, channel scaling and phase mapping.
• Check PTP/time failure and event/disturbance timestamps.

14. Acceptance and uncertainty

A test point’s acceptance band should combine the relay’s declared accuracy/tolerance, algorithm/curve tolerance, test-set uncertainty and project decision rule. Do not simply subtract two rounded display values.

• Use expected-value equations from the correct curve/function.
• Document whether tolerances are additive, relative or absolute.
• Choose points with margin from characteristic intersections where practical.
• For boundary tests, use pass/fail pairs on either side rather than one exact threshold.
• Investigate a result near the limit; do not tune settings to make the template green without engineering approval.
• Preserve raw outputs and calculated values.

15. Changes, retest and regression

1. Record first failure and active configuration.
2. Verify test wiring/template/model before blaming the relay.
3. Open a controlled settings/logic/wiring change.
4. Assess protection coordination and all dependent outputs/interfaces.
5. Download, read back and checksum the revised file.
6. Repeat failed point plus boundary/related functions.
7. Repeat end-to-end trip, alarms/SOE and GOOSE/SCADA dependencies.
8. Keep before/after results and approval.

16. As-left restoration and report

• IED/panel/serial/firmware/settings checksum and active group;
• test boundary/diagram and CT/VT scaling;
• test set/software/template/calibration;
• injected phasors, frequency, binary/GOOSE/SV conditions;
• expected/calculated/actual pickup and timing with tolerance;
• logic/output/breaker/alarm/SOE results;
• raw traces, disturbance files and screenshots with context;
• NCR/change/regression history;
• all outputs unblocked, test/simulation/forces cleared;
• CT/VT blocks, trip circuits and normal SCL/settings restored;
• final read-back/checksum and independent sign-off.

Common mistakes

• Calling relay-terminal injection an end-to-end CT/VT test.
• Testing one point per element.
• Ignoring dropout, direction, restraint and blocking.
• Using wrong CT/VT scaling or phase rotation.
• Stopping at the relay trip LED.
• Combining relay and breaker time without boundaries.
• Trusting a library template without limit review.
• Testing GOOSE normal state only.
• Changing settings to pass without coordination review.
• Leaving output blocks/test modes/forces active.

Official standards and primary references

• IEC 60255-1:2022 — current common requirements for measuring relays/protection equipment.
• IEC 60255-27:2023 — current protection-equipment safety requirements.
• IEC 60255-26:2023 — current EMC requirements for protection equipment.
• IEC 61850-6 consolidated edition, IEC 61850-8-1 consolidated edition and IEC 61850-10:2012+AMD1:2025 — configuration, communication mapping and conformance framework.
• OMICRON CMC 500 official information — current modular parameter/system-based and digital-substation relay-test platform example.
• OMICRON CMC 356 official information — legacy/current-fleet multi-phase relay-test reference, superseded by CMC 500.

Engineering note: The protection study and approved installed settings—not a test library—define intended operation. Secondary injection is strongest when its boundaries and exclusions are explicit. Keep the expected-value calculation, curve equation, tolerance source and raw injection vector with every automated result so a future reviewer can reproduce the decision without the original proprietary template and software.